An Automatic AW-SOM VHDL IP-core Generator

Automatic IP Core generation in SoC

This paper presents performance comparison of two different techniques namely System generator for DSP (Sysgen) and HDL method in Embedded Development Toolkit (EDK) for developing a configurable optimized IP core for signal processing applications. This is performed by implementing and integrating the core in Xilinx System on Chip (SoC) platform with a target board of Xilinx Virtex-II Pro XC2VP...

Image Processing using IP Core Generator through FPGA

Xilinx CORE Generator System generates and delivers parameterizable cores optimized for Xilinx FPGAs. CORE Generator is mainly used to create high density, high performance designs in Xilinx FPGAs in less time. The CORE Generator is included with the ISE WebPack and ISE Foundation software and comes with an extensive library of Xilinx LogiCORE IP. These include DSP functions, memories, storage ...

RTL VHDL Behavioral VHDL Test Generator Behavioral VHDL Simulator VHDL Simulator Switch Level

VHDL Code Generator for a Complex Multiplier

In this paper we present a VHDL code generator for a complex multiplier. The complex multiplier is based on a bit-parallel version of distributed arithmetic which reduces the hardware by nearly half compared to a straightforward implementation based on real multipliers. We choose an Overturned-Stairs adder tree to perform the summations in distributed arithmetic. The tree has a regular structur...

Design and Implementation of Fft Filter Using Vhdl Ip Core Based Design

The FIR FFT core is intended for the signal filtering. With the FIR filter of large impulse response length which exceeds up to Ni = 512 samples. Each FFT iteration dates are computed by the computational unit, called FFTDPATH, another words, data path for FFT calculations. FFTDPATH calculates the radix-2 FFT butterfly in the high pipelined mode. Therefore in each clock cycle one complex number...